Read Aloud the Text Content
This audio was created by Woord's Text to Speech service by content creators from all around the world.
Text Content or SSML code:
The PLL can be used as the basis for frequency synthesizer that can produce a prede series of frequencies that are derived from a stable crystal controlled oscillator. Fig 45 shows the block diagram of frequency synthesizer. It is similar to frequency multiple circuit except that divided by M network is added at the input of phase lock loop. The frequency of the crystal-controlled oscillator is divided by an integer factor M network to produce a frequency fox/M, where fax is the frequency of the cryst controlled oscillator. The VCO frequency fvco is similarly divided by factor N by divide network to give frequency equal to fvoo/N. When the PLL is locked in on divided-down oscillator frequency, we will have fo/Mfco/N, so that frm= (NM) By adjusting divider counts to desired values large number of frequencies can be produced, all derived from the crystal controlled oscillator.